The present specification relates to the fabrication of integrated circuits (ICs). More specifically, the present specification relates to a process of observing alignment or overlay errors associated with tools utilized in IC fabrication. The present specification also relates to alignment patterns for such a process.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). Despite the ability of conventional systems and processes to fabricate millions of devices on an IC, there is still a need to increase the number of devices on an IC.
The increased demand for higher performance integrated circuit (IC) devices has required a higher density of transistors and other components on the IC substrate. The increased density of components, in turn, has required an increase in the number of the layers associated with the IC. Further, as devices have become more complicated, each layer often includes a number of levels of material. For example, a flash memory cell can include a floating gate structure with five or more different levels of material (a gate dielectric, a floating gate, an ONO layer, a control gate, and a silicon layer).
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultra-violet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
The photoresist material or layer associated with conventional lithographic technologies is often utilized to selectively form various IC structures, regions, and layers. Generally, the patterned photoresist material can be utilized to define doping regions, deposition regions, etching regions, or other structures associated with an integrated circuit (IC). A conventional lithographic system is generally utilized to project the pattern to the photoresist material or layer. The photoresist material may be either a positive or a negative photoresist layer.
Registering or aligning the image of one level or layer on an IC to a previously etched, doped, or deposited level or layer of the IC is a significant factor in producing small IC device features. The pattern of the previous level or layer must match (be aligned with) the pattern being formed. When a level or layer is not perfectly aligned, an overlay or alignment error exists and the IC may not function properly. In fact, a limiting characteristic of process fabrication is the aligner fabrication capability, e.g., the overlay accuracy, and machine-to-machine repeatability. The aligner fabrication capability can often be more important to IC fabrication than line width control.
Registration, overlay or alignment errors can be due to several factors. For example, reticles or masks may include overlay errors with respect to each other. In other words, the reticles or masks are not aligned to each other. With this type of overlay error, it is very difficult to realign the masks or reticles through conventional corrective action. Overlay or alignment errors can also be caused by temperature differences between times of exposure, which can cause mask or reticle expansion or contraction so that even perfectly manufactured reticles are not in alignment during IC fabrication. Yet further, alignment tools can often have limited registration capabilities, thereby being another source of alignment errors.
Heretofore, conventional techniques have utilized a rectangle within rectangle (box in a box) technique to measure overlay errors and registration tolerance. According to one conventional technique, a larger rectangle is formed on a previous layer of the IC. A smaller rectangle is formed on a subsequent layer of the IC. If the layers are in alignment, then the smaller rectangle falls within the larger rectangle with appropriate nesting tolerances.
Such nested rectangles can be observed by various conventional inspection equipment. For example, optical inspection equipment can view the larger rectangle and smaller rectangle to ensure that appropriate overlay accuracy has been achieved. However, the use of such equipment adds to the manufacturing time associated with the fabrication of the IC. The overlay measurement requires that the wafer be removed from the commercial semiconductor fabrication equipment and viewed in an inspection tool.
Thus, there is a need to pattern IC devices without requiring complicated overlay error inspections. Further, there is a need to more easily detect overlay errors associated with reticle or mask misalignment. Yet further, there is a need for an alignment pattern which can indicate an overlay error to the naked eye.
An exemplary embodiment relates to a method of observing alignment errors between a first mask or reticle and a second mask or reticle. The first mask or reticle and the second mask or reticle are used in fabricating an integrated circuit. The method includes steps of providing a photoresist layer over a semiconductor substrate, providing a first pattern of radiation to the photoresist layer with the first mask or reticle, providing a second radiation to the photoresist layer with the second mask or reticle, developing the photoresist layer to reveal a plurality of wafer alignment marks, and observing the darkness of the wafer alignment marks.
The first pattern of radiation includes a plurality of first alignment marks. The second pattern of radiation includes a plurality of second alignment marks. The wafer alignment marks are related to a combination of the first alignment marks and the second alignment marks.
Another exemplary embodiment relates to a method of determining an overlay error between a pair of masks or reticles used to fabricate an integrated circuit. The method includes providing a pattern of radiation to a substrate with a first mask or reticle, and providing a pattern of radiation to the substrate with a second mask or reticle. The method also includes providing a plurality of alignment features on the substrate. The alignment features are related to the first mask or reticle and the second mask or reticle. A characteristic of the alignment features can be observed via the naked eye to determine the overlay error between the first mask or reticle and the second mask or reticle.
Still another exemplary embodiment relates to a method of determining an overlay error with the naked eye between a first mask or reticle and a second mask or reticle. The first mask or reticle and the second mask or reticle are utilized to fabricate an integrated circuit. The method includes forming a set of alignment marks on a substrate and observing the darkness characteristic of the alignment marks with the naked eye. The alignment marks are related to alignment patterns associated with the first mask or reticle and the second mask or reticle. The set of alignment marks have a darkness characteristic related to the overlay error.